The present invention relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit capable of reducing power consumption.
Generally, a Delay Locked Loop (DLL) circuit controls a timing of data outputted from a memory device, e.g., a synchronous semiconductor memory device, by using an external clock inputted from the outside of the memory device.
In order to transfer the output data of the semiconductor memory device to a chip set without an error, the semiconductor memory device and the chip set should be synchronized with the external clock. However, since the external clock inputted to the semiconductor memory device is delayed by an internal circuit of the semiconductor memory device, a phase difference is generated between the external clock and an internal clock. The DLL circuit compensates the clock skew generated by the internal circuit of the semiconductor memory device in order to eliminate the phase difference between the data outputted from the semiconductor memory device and the clock.
FIG. 1 is a block diagram depicting a conventional delay locked loop circuit.
As shown in the drawing, the conventional delay locked loop circuit includes a first delay locking unit 101, a second delay locking unit 111 and a duty ratio compensation unit 121.
The first delay locking unit 101 includes a first phase comparison unit 103, a first delay control unit 105 and a first replica model unit 107. The second delay locking unit 111 includes a second phase comparison unit 113, a second delay control unit 115 and a second replica model unit 117.
The first phase comparison unit 103 compares a phase of an external clock EXT_CLK with that of a first feedback clock FB_1 outputted from the first replica model unit 107 in order to generate a first comparison signal CMP_1 which includes information about a phase difference between the external clock EXT_CLK and the first feedback clock FB_1. A clock delay component inside a semiconductor device is modeled in the first replica model unit 107. The first replica model unit 107 receives a first internal clock CLKOUT_1 whose duty ratio is compensated by a second compensation unit 125 mentioned later in order to output the first feedback clock FB_1.
The first comparison signal CMP_1 is inputted to the first delay control unit 105. The first delay control unit 105 outputs a first internal clock CLK_1 by delaying a compensated external clock CLK_CC generated by a first compensation unit 123 mentioned later based on the first compensation signal CMP_1. Herein, the first compensation unit 123 generates the compensated external clock CLK_CC by compensating a duty ratio of the external clock EXT_CLK.
As a result, through the above-mentioned processes, delays due to the first delay control unit 105 and the first replica model unit 107 are reflected to the first feedback clock FB_1, and thus a phase of the first feedback clock FB_1 is synchronized with that of the compensated external clock CLK_CC. At this time, the first internal clock CLK_1, to which a delay due to the first delay control unit 105 is reflected, is delay-locked, i.e., a locking is completed.
The second delay locking unit 111 performs a similar operation to the first delay locking unit 101 in order to synchronize a phase of the external clock EXT_CLK with that of a second feedback clock FB_2 and output a second delay-locked internal clock CLK_2. However, since the second delay control unit 115 outputs the second internal clock CLK_2 after inverting it, a rising edge of the second internal clock CLK_2 is synchronized with that of the first internal clock CLK_1 and a duty ratio of the second internal clock CLK_2 is opposite to that of the first internal clock CLK_1. That is because the second delay control unit 115 performs an operation related to a duty ratio compensating operation of the second compensation unit 125 mentioned later. In FIG. 1, the circle at the output terminal of the second delay control unit 115 means an inversion.
The duty ratio compensation unit 121 includes the first compensation unit 123, the second compensation unit 125, a duty ratio sensing unit 127 and a compensation control unit 129.
The duty ratio compensating operation is performed after the locking operation and is controlled by the compensation control unit 129. After the locking operation, the compensation control unit 129 activates a compensation signal DCC_EN so that the duty ratio compensating operation is performed by the first and second compensation units 123 and 125 in response to the compensation signal DCC_EN.
The duty ratio sensing unit 127 detects duty ratios of the first and second internal clocks CLK_1 and CLK_2 in order to generate a detection signal PD. The compensation control unit 129 outputs a control signal DCC_CTRL which includes duty ratio adjustment information to the compensation unit 123 in response to the detection signal PD. The first compensation unit 123 compensates a duty ratio of the external clock EXT_CLK in order to generate the compensated external clock CLK_CC in response to the control signal DCC_CTRL.
The second compensation unit 125 mixes phases of falling edges of the first and second internal clocks CLK_1 and CLK_2 to a medium phase in order to output the duty ratio compensated first and second internal clocks CLKOUT_1 and CLKOUT_2. The second compensation unit 125, unlike the first compensation unit 123, is operated only when a dual compensation signal DUAL_EN inputted from the outside of the conventional delay locked loop circuit is activated. In case of improving a duty ratio compensating ability of the conventional delay locked loop circuit, the dual compensation signal DUAL_EN can be set to be activated.
After completing the locking operation and the duty ratio compensating operation through the above-mentioned processes, the first and second internal clocks CLKOUT_1 and CLKOUT_2 are kept in the completed state of the locking and duty ratio compensating operations. Thereafter, the conventional delay locked loop circuit performs an updating process to output the first and second internal clocks CLKOUT_1 and CLKOUT_2 by periodically reflecting a change.
FIG. 2 is a diagram illustrating an operation of the conventional delay locked loop circuit shown in FIG. 1 when the dual compensation signal DUAL_EN is deactivated. The arrow indicates an enablement of each unit at each operation step of the conventional delay locked loop circuit.
If the operation of the conventional delay locked loop circuit is started, the first and second internal clocks CLK_1 and CLK_2 are delay-locked by the first and second delay locking units 101 and 111 respectively. Thereafter, the duty ratio compensating operation is performed by the first compensation unit 123. Since the first and second delay locking units 101 and 111 are still enabled after the locking operation, the duty ratio sensing unit 127 generates the detection signal PD by detecting duty ratios of the first and second internal clocks CLK_1 and CLK_2, and the first compensation unit 123 compensates a duty ratio of the external clock EXT_CLK in response to the control signal DCC_CTRL.
In case the dual compensation signal DUAL_EN is deactivated, unlike when the dual compensation signal DUAL_EN is activated, the operation of the conventional delay locked loop circuit is not influenced, even if the second delay locking unit 111 is disabled except for the update process after the completion of the duty ratio compensation. However, as shown in the drawing, even after the duty ratio compensating operation of the first compensation unit 123 is completed, the second delay locking unit 111 is still enabled. Since the compensated external clock CLK_CC inputted to the second delay control unit 115 continuously toggles, unwanted power consumption occurs in the second delay control units 115.
As a result, according to the conventional delay locked loop circuit, even when the second compensation unit 125 is not operated, the second delay locking unit 111 is still enabled, thereby unnecessarily consuming power after the completion of the duty ratio compensating operation.